(1) Field of the Invention
The present invention relates to a semiconductor device and a method for fabricating the same, and more particularly relates to a semiconductor device, such as a dynamic random access memory (DRAM) device, having a stacked capacitor structure obtained by stacking films constituting a memory cell capacitor above a transistor and a method for fabricating the same.
(2) Description of Related Art
In recent years, attempts have been made to meet the need for increasing storage capacity in DRAM devices by increasing the storage capacity of memory cells per unit area occupied in a DRAM chip to decrease the area occupied by the memory cells and reduce the DRAM chip size.
As a stacked capacitor structure of a known DRAM device, a capacitor electrode structure has been suggested in which an interlayer insulating film formed on a MIS transistor has a trench part and a lower electrode of a concave shape in cross section is formed on the trench part (see, for example, Japanese Unexamined Patent Publication No. 10-79478).
FIG. 5 shows the cross-sectional structure of a known semiconductor device having a stacked capacitor structure. As shown in FIG. 5, the known semiconductor device comprises a plurality of MIS transistors 100 and capacitors 122. The MIS transistors 100 are formed on active regions of the principal surface of a semiconductor substrate 101 defined by a shallow trench isolation 102, respectively, and serve as switch transistors. The capacitors 122 are formed above the corresponding MIS transistors 100 with a first interlayer insulating film 107 interposed therebetween.
Each MIS transistor 100 is composed of a gate insulating film 103 formed on each active region of the semiconductor substrate 101, a gate electrode 104 formed thereon, insulative sidewalls 105 formed on the side surfaces of the gate electrode 104, and a source region 106A and a drain region 106B formed in the upper part of the active region.
The capacitor 122 is formed by successively stacking a lower electrode 111, a capacitive insulating film 112 and an upper electrode 113 of concave shapes in cross section on a trench part 110 of a second interlayer insulating film 109 formed on the first interlayer insulating film 107 covering each MIS transistor 100. The lower electrode 111 is electrically connected to the source region 106A of the MIS transistor 100 through a first plug 108A formed in the first interlayer insulating film 107.
A third interlayer insulating film 114 is formed on the second interlayer insulating film 109 to cover the capacitor 122, and a bit interconnect 119 is formed on the third interlayer insulating film 114. The bit interconnect 119 is electrically connected to the drain region 106B of the MIS transistor 100 through a second plug 108B formed in the first interlayer insulating film 107 and a third plug 118 formed in the third interlayer insulating film 114 and the second interlayer insulating film 109.
Next, FIGS. 6A through 6D show process steps in a known method for fabricating a semiconductor device having a stacked capacitor structure. They show only a method for fabricating the capacitor 122.
First, in a process step shown in FIG. 6A, a source region 106A of an unshown MIS transistor is formed in an active region of a semiconductor substrate 101 by ion implantation, and then a first interlayer insulating film 107 is formed to cover the MIS transistor. Subsequently, a contact hole is formed in the first interlayer insulating film 107 to expose the source region 106A, and the formed contact hole is filled with a conductive film to form a first plug 108A. Thereafter, a second interlayer insulating film 109 is formed on the first plug 108A and the first interlayer insulating film 107, and then a trench part 110 is formed in a region of the second interlayer insulating film 109 where a capacitor is to be formed (hereinafter, referred to as a “capacitor formation region”) to expose the first plug 108A.
Next, in a process step shown in FIG. 6B, a polysilicon film 111A doped with impurities is formed on the entire surface of the second interlayer insulating film 109 including the trench part 110. Thereafter, the entire surface of the second interlayer insulating film 109 including the trench part 110 is coated with a resist film 120. Subsequently, the coated resist film 120 is etched back by anisotropic dry etching to leave a part of the resist film 120 only inside the trench part 110 in the capacitor formation region.
Next, in a process step shown in FIG. 6C, a part of the polysilicon film 111A located on the top surface of the second interlayer insulating film 109 is removed by anisotropic dry etching using the resist mask 120 as a mask. In this way, a lower electrode 111 of a concave shape in cross section is formed inside the trench part 110 of the second interlayer insulating film 109.
Next, in a process step shown in FIG. 6D, after the removal of the resist film 120, an insulating film for a capacitance and a conductive film for an upper electrode are formed on the second interlayer insulating film 109 and the lower electrode 111. Thereafter, the insulating film for a capacitance and the conductive film for an upper electrode are patterned into a capacitive insulating film 112 and an upper electrode 113, respectively. In this way, a capacitor 112 is composed of the lower electrode 111, the capacitive insulating film 112 and the upper electrode 113.
According to the known method for fabricating the capacitor 122, since as described above the lower electrode 111 has a concave shape in cross section, the side surface area of the capacitor 122 increases, resulting in the increased storage capacity per unit area occupied.